Kingston 32GB 1333MHz DDR3 Server Memory
Scan code: LN58222
Manufacturer code: KVR13LL9Q4/32
End Of Life
Kingston 32GB 1333MHz DDR3 Server Memory
32GB (1x32) Kingston 1333MHz DDR3, PC3L-10600, 4Rx4, 4G x 72-Bit, 8-Bit pre-fetch, 1.35V
Scan code:
LN58222
Manufacturer code:
KVR13LL9Q4/32
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Product Overview
32GB Kingston 1333MHz DDR3 Server Memory
This document describes ValueRAM's 4G x 72-bit (32GB) DDR3L-1333 CL9 SDRAM (Synchronous DRAM), low voltage, load reduced 4Rx4 ECC memory module, based on thirty-six DDP 2G x 4-bit components. The SPD is programmed to JEDEC standard latency DDR3-1333 timing of 9-9-9 at 1.35V and 1.5V. This 240-pin LRDIMM uses gold contact fingers. The electrical and mechanical specifications are as follows:
• JEDEC standard 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~1.575V) Power Supply
• VDDQ = 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~ 1.575V)
• 667MHz fCK for 1333Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 9, 8, 7, 6
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 7 (DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either on the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• On-DIMM thermal sensor (Grade B)
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95°C
• Asynchronous Reset
• PCB : Height 1.180” (30.00mm), double sided component Features • CL(IDD) 9 cycles
• Row Cycle Time (tRCmin) 49.125ns (min.)
• Refresh to Active/Refresh 260ns (min.)
• Command Time (tRFCmin)
• Row Active Time (tRASmin) 36ns (min.)
• Operating Power (Idd3_Active) (1.35V) = 11 W*
• UL Rating 94 V - 0
• Operating Temperature 0oC to 85oC
• Storage Temperature -55o C to +100oC
This document describes ValueRAM's 4G x 72-bit (32GB) DDR3L-1333 CL9 SDRAM (Synchronous DRAM), low voltage, load reduced 4Rx4 ECC memory module, based on thirty-six DDP 2G x 4-bit components. The SPD is programmed to JEDEC standard latency DDR3-1333 timing of 9-9-9 at 1.35V and 1.5V. This 240-pin LRDIMM uses gold contact fingers. The electrical and mechanical specifications are as follows:
• JEDEC standard 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~1.575V) Power Supply
• VDDQ = 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~ 1.575V)
• 667MHz fCK for 1333Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 9, 8, 7, 6
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 7 (DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either on the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• On-DIMM thermal sensor (Grade B)
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95°C
• Asynchronous Reset
• PCB : Height 1.180” (30.00mm), double sided component Features • CL(IDD) 9 cycles
• Row Cycle Time (tRCmin) 49.125ns (min.)
• Refresh to Active/Refresh 260ns (min.)
• Command Time (tRFCmin)
• Row Active Time (tRASmin) 36ns (min.)
• Operating Power (Idd3_Active) (1.35V) = 11 W*
• UL Rating 94 V - 0
• Operating Temperature 0oC to 85oC
• Storage Temperature -55o C to +100oC