DDR / DDR2

Some other new technologies are incorporated into DDR2 also. With DDR, excess signal noise, reflected signals and other interference is eliminated by motherboard based transistors. DDR2 differs in that these terminating transistors are removed from the motherboard and are instead built into each memory module, allowing excess noise to be eliminated faster, this technology is called On Die Termination (ODT).

Another method of increasing signal integrity is OCD (Off Chip Driver calibration), which helps maintain the signal by smoothing voltages and supplying a reference voltage and is again built into the modules. Posted CAS and Additive Latency both aid in preventing data collisions within the module whilst allowing a greater number of read/write transactions per clock cycle increasing efficiency.

Two other things to take from the table are the increased CAS latency (CL) and reduced operating voltage. The change in CAS latency is required to offset the speed increase. Whether this increase greatly affects performance remains to be seen. Early samples did suffer from higher latency and in some cases were slower than their DDR relatives, however technology has moved on since then and newer models are running with much lower latencies and with the increased performance this brings. The operating voltage required by DDR2 modules is much reduced meaning less voltage is required to read from and write to the memory, another indication of increased efficiency.

CAS stands for Column Address Strobe, and Latency is defined as the amount of time between a stimulus and a response; to use another analogy: a RAM module can be compared to a spreadsheet, but with “memory” cells in place of numbers and formulae, with each cell possessing a cell address derived from its column and row position. As expected and inline with the analogy there also exists RAS latency or Row Address Strobe. To fetch data the chipset accesses the desired row of the memory “spreadsheet” by placing the required cell address on the memory address pins and switching on the RAS signal. The time in clock cycles taken to process this instruction is known as RAS to CAS delay, once complete the column address is fed into the address pins and the CAS signal made active to allow the correct column of your memory spreadsheet to be accessed, once again a few clock cycles pass before the data is available on the memory pins.

This delay between addressing the column pins and the data being available is CAS latency. With CAS 2, two clock cycles pass before the data is ready and with CAS 3, three clock cycles pass. This is not to say, however, that a CAS 2 module is a third faster than CAS 3, as other factors also affect how quickly data is retrieved. In essence, however, lower CAS latencies generally mean better performance as data can be accessed in a shorter amount of time.