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Intel’s Core 2 Duo is now slugging it out against AMD’s Socket AM2 Athlon 64s with DDR2 memory support. So what is next on the roadmap from the two chip-vending foes?
Intel lost the performance high ground to AMD for a couple of years. It still had the lion’s share of the market, but AMD’s Athlon 64 could beat anything Intel’s Pentium 4 had to offer, in both single- and dual-core variations. This all changed with the introduction of the Core Microarchitecture in the middle of 2006. Almost overnight, Intel won back benchmark supremacy from AMD.
With such a radical change of direction as the Core Microarchitecture, Intel isn’t expected to make any other major changes to its core design for the next year or so. There will be an even more budget version of the Core 2 Duo called the E4300 early next year, and the Pentium brand will return with a single-core Core Microarchitecture range for extremely low-cost PCs. The biggest change is the move from dual-core to quad-core, which has already begun.
As with its Pentium D, Intel’s first quad-core processors are essentially two processor dies packaged into one socket. Where the Pentium D consists of two Pentium 4s sitting side-by-side, the Intel Core 2 Extreme QX6700 and Core 2 Quad Q6600 are based on a pair of Core 2 Duos packaged together. This means that although cores on the same die can share Level 2 SmartCache, the two pairs can only communicate across the Front Side Bus.
Somewhere in the second half of 2007, however, Intel is expected to launch a quad-core chip with all four cores on the same physical processor die. These will also share a single 6MB SmartCache. However, the cores themselves are expected to be fairly minor revisions of the Core Microarchitecture, not a major overhaul.
Towards the end of 2007, Intel is expected to release another update of the Core Microarchitecture, currently codenamed Penryn. This will move to a 45nm process (see below), but will initially consist of essentially the same Core Microarchitecture design. However, the smaller core size will be Intel’s cue to launch its next coup – eight cores on a single processor. The eight-core chip will allegedly sport up to 12MB of cache, but is expected to consist of two quad-core chips packaged together.
AMD fights back
AMD’s first response to Intel’s Core Microarchitecture was the Rev F core, which upgraded the DDR memory controller used in all previous Athlon 64s and Opterons to DDR2. However, one area where Intel has had a lead over AMD since long before the Core Microarchitecture arrived is in its manufacturing process. Intel has been shipping processors produced using a 65nm process since the Pentium XE 955 in late 2005. This means the individual logic gates are smaller than processors produced using a 90nm process, which reduces the power consumption and allows them to operate at a higher frequency.
AMD’s Rev F processors are still manufactured using a 90nm process, but Rev G moves to 65nm at last. The Rev G isn’t just a ‘die shrink’, though, where the existing processor is simply scaled down. The new core also includes an extra complex decoder, an out of order load/store buffer and an out of order read/write buffer. These improve the amount of real work the processor can perform per clock cycle. Certain ranges will also include a DDR2-800 controller rather than the DDR2-667 of the Rev F.
Next in line is the Rev H, codenamed Barcelona and expected to be branded the Athlon 64 X4, which is AMD’s first quad-core part. AMD is moving straight to four cores on one die, rather than packaging two together. The Rev H is also a rather different architecture to Intel’s dual- and quad-core processors. As with the Athlon 64 X2, each core will retain its own individual 512KB of Level 2 cache, which can be shared with the other cores over a System Request Queue running at core speed. However, Barcelona will also see a return of the Level 3 cache. There will be 2MB of this, which will be shared dynamically between all four cores.
By the end of 2007, AMD is expected to release another update of
its quad-core processor, codenamed Budapest. This will incorporate
an on-die memory controller capable of supporting both DDR2 and
DDR3, depending on the host motherboard design. It will also support
HyperTransport 3, for extremely fast communications with peripherals
and other processors in a multi-socket configuration.