AMD 252 Opteron 64 Processor
AMD Opteron 64 252, Socket 940, Troy Core, 2.6GHz, 1MB Cache, 92.6W, CPU, OEM
£59.99
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By DPD On 31st Jul 2017
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Product Overview
The AMD Opteron processor provides a breakthrough in high-performance, low power processing for edge-of-enterprise markets including storage and telecommunications, as well as more traditional embedded markets such as security and medical imaging, military systems, and single-board computing. Features
• Compatible with Existing 32-Bit Code Base: Including support for SSE, SSE2, MMX™, 3DNow! ™ technology and legacy x86 instructions.
• Integrated Memory Controller: 144-bit DDR SDRAM at 100, 133, and 166 MHz.
• HyperTransport™ Technology to I/O Devices: Three links, 16-bits in each direction, each supports up to 1000 MT/s or 2 GB/s in each direction. Each link can connect to an I/O device or another processor.
• 64-Kbyte 2-Way Associative ECC-Protected L1 Data Cache
• 64-Kbyte 2-Way Associative Parity-Protected L1 Instruction Cache with advanced branch prediction.
• 1024-Kbyte (1-Mbyte) 16-Way Associative ECC-Protected L2 Cache Exclusive cache architecture—storage in addition to L1 caches.
• ACPI 2.0 compliant.
• Power Supplies: VDD (core): 1.35-V at 52 Amps (max), Target CPU Core Power: 92.6 Watts.
Electrical Interfaces:
• HyperTransport technology: LVDS-Like differential, unidirectional.
• DDR SDRAM: SSTL_2 per JEDEC specification.
• Clock, reset, and test signals also use DDR SDRAM-like electrical specifications.
Packaging:
• 940-pin lidded ceramic micro PGA.
• 1.27-mm pin pitch.
• 31x31 row pin array.
• 40mm x 40mm ceramic substrate.
• Ceramic C4 die attach.
• Integrated Memory Controller: 144-bit DDR SDRAM at 100, 133, and 166 MHz.
• HyperTransport™ Technology to I/O Devices: Three links, 16-bits in each direction, each supports up to 1000 MT/s or 2 GB/s in each direction. Each link can connect to an I/O device or another processor.
• 64-Kbyte 2-Way Associative ECC-Protected L1 Data Cache
• 64-Kbyte 2-Way Associative Parity-Protected L1 Instruction Cache with advanced branch prediction.
• 1024-Kbyte (1-Mbyte) 16-Way Associative ECC-Protected L2 Cache Exclusive cache architecture—storage in addition to L1 caches.
• ACPI 2.0 compliant.
• Power Supplies: VDD (core): 1.35-V at 52 Amps (max), Target CPU Core Power: 92.6 Watts.
Electrical Interfaces:
• HyperTransport technology: LVDS-Like differential, unidirectional.
• DDR SDRAM: SSTL_2 per JEDEC specification.
• Clock, reset, and test signals also use DDR SDRAM-like electrical specifications.
Packaging:
• 940-pin lidded ceramic micro PGA.
• 1.27-mm pin pitch.
• 31x31 row pin array.
• 40mm x 40mm ceramic substrate.
• Ceramic C4 die attach.
