Scan code:
LN8279
Manufacturer code:
AMD 1 to 2-Way Opteron 246 (2000MHz) 64Bit CPU
AMD 1 to 2-Way Opteron 246 (2000MHz), 64Bit CPU, 1024L2 Cache, Compatible with 32-Bit Code Base, Memory Controller, OEM
Scan code:
LN8279
Manufacturer code:
Order now and get it tomorrow, Fri 18th Jun
From
£9.70
/ month (APR 14.9%)
spend over £280 and Buy Now, Pay Later or spread the cost of your finance over 24-48 months with a 10% deposit.
Delivery Options
- By DPD On 18th Jun to your specified address. | £5.48 Receive SMS with one-hour delivery window Weekend, timed and European delivery options are available at checkout
- Collect instore Collect from our Bolton store, BL6 6PE | Free
- UPS and DPD Pickup Pickup from local convenience store | £4.79
Product Overview
Compatible with Existing 32-Bit Code Base
• Including support for SSE, SSE2, MMX™, 3DNow!™ technology and legacy x86 instructions.
• Runs existing operating systems and drivers.
• Local APIC on-chip.
AMD 64-Bit Technology
• AMD’s 64-bit x86 instruction set extensions.
• 64-bit integer registers, 48-bit virtual addresses, 40-bit physical addresses.
• Eight new 64-bit integer registers (16 total).
• Eight new 128-bit SSE/SSE2 registers (16 total).
Integrated Memory Controller
• Low-latency, high-bandwidth.
• 144-bit DDR SDRAM at 100, 133, and 166 MHz.
HyperTransport™ Technology to I/O Devices
• Three links, 16-bits in each direction, each supports up to 1600 MT/s or 3.2 GB/s in each direction.
• Each link can connect to an I/O device or another processor.
64-Kbyte 2-Way Associative ECC-Protected L1 Data Cache
• Two 64-bit operations per cycle, 3-cycle latency.
64-Kbyte 2-Way Associative Parity-Protected L1 Instruction Cache
• With advanced branch prediction.
1024-Kbyte (1-Mbyte) 16-Way Associative ECC-Protected L2 Cache
• Exclusive cache architecture—storage in addition to L1 caches.
Machine Check Architecture
• Includes hardware scrubbing of major ECCprotected arrays.
Power Management
• Multiple low-power states.
• System Management Mode (SMM).
• ACPI 2.0 compliant.
Power Supplies
• VDD (core): 1.55-V at 52 Amps (max).
• VDDIO: 2.5-V at 2.9 Amps (max) for DDR SDRAM I/O.
• VLDT: 1.2-V at 1.5 Amps for HyperTransport™ technology interface.
• VTT: 1.25-V at 0.2 Amps required for 2.5-V I/Os.
• Target CPU Core Power: 80.6 Watts.
• Target Maximum Thermal Power: 84.7 Watts.
Electrical Interfaces
• HyperTransport technology: LVDS-Like differential, unidirectional.
• DDR SDRAM: SSTL_2 per JEDEC specification.
• Clock, reset, and test signals also use DDR SDRAM-like electrical specifications.
Packaging
• 940-pin lidded ceramic micro PGA.
• 1.27-mm pin pitch.
• 31x31 row pin array.
• 40mm x 40mm ceramic substrate.
• Ceramic C4 die attach.
This CPU is certified for SLI use. Features • Compatible with Existing 32-Bit Code Base.
• AMD 64-Bit Technology.
• Integrated low-latency, high-bandwidth Memory Controller.
• 64-Kbyte 2-Way Associative ECC-Protected L1 Data Cache.
• 64-Kbyte 2-Way Associative Parity-Protected L1 Instruction Cache.
• 1024-Kbyte (1-Mbyte) 16-Way Associative ECC-Protected L2 Cache.
• Multiple low-power states.
• Including support for SSE, SSE2, MMX™, 3DNow!™ technology and legacy x86 instructions.
• Runs existing operating systems and drivers.
• Local APIC on-chip.
AMD 64-Bit Technology
• AMD’s 64-bit x86 instruction set extensions.
• 64-bit integer registers, 48-bit virtual addresses, 40-bit physical addresses.
• Eight new 64-bit integer registers (16 total).
• Eight new 128-bit SSE/SSE2 registers (16 total).
Integrated Memory Controller
• Low-latency, high-bandwidth.
• 144-bit DDR SDRAM at 100, 133, and 166 MHz.
HyperTransport™ Technology to I/O Devices
• Three links, 16-bits in each direction, each supports up to 1600 MT/s or 3.2 GB/s in each direction.
• Each link can connect to an I/O device or another processor.
64-Kbyte 2-Way Associative ECC-Protected L1 Data Cache
• Two 64-bit operations per cycle, 3-cycle latency.
64-Kbyte 2-Way Associative Parity-Protected L1 Instruction Cache
• With advanced branch prediction.
1024-Kbyte (1-Mbyte) 16-Way Associative ECC-Protected L2 Cache
• Exclusive cache architecture—storage in addition to L1 caches.
Machine Check Architecture
• Includes hardware scrubbing of major ECCprotected arrays.
Power Management
• Multiple low-power states.
• System Management Mode (SMM).
• ACPI 2.0 compliant.
Power Supplies
• VDD (core): 1.55-V at 52 Amps (max).
• VDDIO: 2.5-V at 2.9 Amps (max) for DDR SDRAM I/O.
• VLDT: 1.2-V at 1.5 Amps for HyperTransport™ technology interface.
• VTT: 1.25-V at 0.2 Amps required for 2.5-V I/Os.
• Target CPU Core Power: 80.6 Watts.
• Target Maximum Thermal Power: 84.7 Watts.
Electrical Interfaces
• HyperTransport technology: LVDS-Like differential, unidirectional.
• DDR SDRAM: SSTL_2 per JEDEC specification.
• Clock, reset, and test signals also use DDR SDRAM-like electrical specifications.
Packaging
• 940-pin lidded ceramic micro PGA.
• 1.27-mm pin pitch.
• 31x31 row pin array.
• 40mm x 40mm ceramic substrate.
• Ceramic C4 die attach.
This CPU is certified for SLI use. Features • Compatible with Existing 32-Bit Code Base.
• AMD 64-Bit Technology.
• Integrated low-latency, high-bandwidth Memory Controller.
• 64-Kbyte 2-Way Associative ECC-Protected L1 Data Cache.
• 64-Kbyte 2-Way Associative Parity-Protected L1 Instruction Cache.
• 1024-Kbyte (1-Mbyte) 16-Way Associative ECC-Protected L2 Cache.
• Multiple low-power states.
AMD 1 to 2-Way Opteron 246 (2000MHz) 64Bit CPU
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