Hynix 2GB DDR3 PC3-8500 (1066) Single Channel Server Memory
Scan code: LN27473
Manufacturer code: HMT125U7BFR8C-G7T0
End Of Life
Hynix 2GB DDR3 PC3-8500 (1066) Single Channel Server Memory
2GB Hynix Server Memory, DDR3, PC3-8500 (1066MHz), 240 Pin, ECC, Unbuffered, CAS 7-7-7, PC/Apple
Scan code:
LN27473
Manufacturer code:
HMT125U7BFR8C-G7T0
This product is no longer available to purchase.
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Product Overview
Apple Xserve - Early 2009
Compatible as well as PC
DDR3 SDRAM, which upholds the next generation main memory standard, can transfer data twice as fast as the current generation DRAM. Hynix's DDR3 SDRAM boasts high performance and low power consumption. It supports data transfer rate up to 1.6Gb/s and operate at a voltage as low as 1.5V comparable to DDR2 which a previous version of DDR3. Hynix's DDR3 also featuring functions such as 2Q calibrations, fly-by topology, dynamic on-die-termination and write levelization to ensure signal integrity and thus higher performance. Features • VDD=VDDQ=1.5V
• Fully differential clock inputs (CK, /CK) operation
• Differential Data Strobe (DQS, /DQS)
• On chip DLL align DQ, DQS and /DQS transition with CK transition
• DM masks write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• BL switch on the fly
• 8banks
• 8K refresh cycles /64ms
• DDR3 SDRAM Package : JEDEC standard 82ball FBGA(x4/x8) , 100ball FBGA(x16) with support balls
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• Auto Self Refresh supported
• 8 bit pre-fetch
Compatible as well as PC
DDR3 SDRAM, which upholds the next generation main memory standard, can transfer data twice as fast as the current generation DRAM. Hynix's DDR3 SDRAM boasts high performance and low power consumption. It supports data transfer rate up to 1.6Gb/s and operate at a voltage as low as 1.5V comparable to DDR2 which a previous version of DDR3. Hynix's DDR3 also featuring functions such as 2Q calibrations, fly-by topology, dynamic on-die-termination and write levelization to ensure signal integrity and thus higher performance. Features • VDD=VDDQ=1.5V
• Fully differential clock inputs (CK, /CK) operation
• Differential Data Strobe (DQS, /DQS)
• On chip DLL align DQ, DQS and /DQS transition with CK transition
• DM masks write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• BL switch on the fly
• 8banks
• 8K refresh cycles /64ms
• DDR3 SDRAM Package : JEDEC standard 82ball FBGA(x4/x8) , 100ball FBGA(x16) with support balls
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• Auto Self Refresh supported
• 8 bit pre-fetch
