Hynix 2GB DDR3 PC3-10600 (1333) Single Channel Server Memory
Scan code: LN27476
Manufacturer code: HMT125U7TFR8C-H9T0-C
End Of Life
Hynix 2GB DDR3 PC3-10600 (1333) Single Channel Server Memory
2GB Hynix, Server Memory, DDR3, PC3-10600 (1333MHz), 240 Pin, ECC, un-buffered, CAS 9-9-9, PC/Apple
Scan code:
LN27476
Manufacturer code:
HMT125U7TFR8C-H9T0-C
This product is no longer available to purchase.
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Product Overview
SK Hynix unbuffered Dual In-Line Memory Module(DIMM). DDR3 SDRAM in Fine Ball Grid Array(FBGA) package on a 240 pin glass-epoxy substrate.
Features
• VDD=VDDQ=1.5V
• VDDSPD=3.3V to 3.6V
• Fully differential clock inputs (CK, /CK) operation
• Differential Data Strobe (DQS, /DQS)
• On chip DLL align DQ, DQS and /DQS transition with CK transition
• DM masks write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported
• Programmable additive latency 0, CL-1, and CL-2 supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• BL switch on the fly
• 8banks
• 8K refresh cycles /64ms
• DDR3 SDRAM Package : JEDEC standard 82ball FBGA(x4/x8) , 100ball FBGA(x16) with support balls
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• Auto Self Refresh supported
• On Die Thermal Sensor supported ( JEDEC optional )
• 8 bit pre-fetch
• This product is in compliance with RoHS.
• VDDSPD=3.3V to 3.6V
• Fully differential clock inputs (CK, /CK) operation
• Differential Data Strobe (DQS, /DQS)
• On chip DLL align DQ, DQS and /DQS transition with CK transition
• DM masks write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported
• Programmable additive latency 0, CL-1, and CL-2 supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• BL switch on the fly
• 8banks
• 8K refresh cycles /64ms
• DDR3 SDRAM Package : JEDEC standard 82ball FBGA(x4/x8) , 100ball FBGA(x16) with support balls
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• Auto Self Refresh supported
• On Die Thermal Sensor supported ( JEDEC optional )
• 8 bit pre-fetch
• This product is in compliance with RoHS.
